1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a late-write type semiconductor memory device like a high speed static RAM (hereinafter referred to as SRAM).
2. Description of the Prior Art
A late-write type SRAM is one of a variety of prior arts concerning a synchronous type semiconductor memory device for high speed operations, where a total time required for write data reduces, resulting in an effect of improving margin of a write operation. One such SRAM is disclosed in U.S. Pat. No. 5,717, 653.
The semiconductor memory device delays a write address input from outside for a number of cycles in the course of performing a late-write process to input to an address decoder and to select word line and bit line. After the write address is input and delayed by a number of cycles, the data input signal input from outside is transmitted to a write driver. Then, the write operation is actuated after a number of cycles. In other words, for instance, in a two cycle late-write process of the semiconductor memory device, write data is input to perform the write operation after a write address is input and delayed by two cycles.
In addition, the conventional semiconductor memory device for high speed operation includes other functions like bypass operation as well as late-write operation. If a write command proceeds to a read command for a number of cycles and both of the write address and read address are identical, the semiconductor memory device performs a bypass operation by immediately outputting the previous write data through the data output buffer without going through a normal read operation of memory cells. However, in such devices there have been a number of data output errors in the high speed operation, rather than in the bypass operation. Some of the causes of these problems are described in detail later in this document. Therefore, the aforementioned data output errors make it difficult to reduce in the time interval of cycles in the bypass operation, so that the semiconductor memory device can not perform at high-speed operation. This limits efforts in improving the performance of the whole system.